INFOPAD Wireless Systems Design
In order to support the tremendous per-user capacity that the Infopad
downlink
requires, we undertook an effort to design a new wireless system
loosely based on the IS-95 digital cellular standard. Our target
goals were to meet the requirements of a sustained 2 Mbps/user throughput,
for a maximum per-cell capacity of 100 Mbps, as well as considerations of
monolithic implementability and minimum power consumption.
The exact system specification is as follows:
- Code-division multiple-access
- User-division via Walsh sequence coding (intracell)
- Cell-cell isolation via PN sequence coding (intercell)
- Differential quadrature phase-shift key symbol encoding
- 124 Mbps (64 Mbaud) aggregate system data rate, divided into
- 62 parallel 2 Mbps streams
- 1 pilot channel
- 1 setup/teardown control channel
- 1.088 GHz carrier
- 85 MHz 99% transmit bandwidth
- 30% excess bandwidth, raised-cosine pulse-shape
- Raw link BER ~ .001 to .0001
The Rogues Gallery of INFOPAD Custom Chips
Complete integrated RF receiver front-end
- Low-noise 1 GHz amplifier
- Symmetric dual I/Q receive path
- Differential preamp
- Homodyne sampling demodulator
- Switched-capacitor AGC chain
- 1b-3b pipelined 128 MHz A/D
I/Q Sampling demodulator test circuit
- Differential preamp
- Homodyne sampling demodulator
3b Flash A/D test circuit
- Sampling demodulator front-end
- Single switched-capacitor latch
- 3b flash A/D
Digital modulator/pulse shaping filter
- 15 parallel user streams + 1 pilot channel
- DQPSK modulator, plus per-user Walsh encoding (length 64)
- PN modulator (length 32768, based on a 16-tap shift-register sequence)
- 30% excess BW raised-cosine pulse shaping filter
- 40 tap FIR filter
- 4 parallel subfilters
- Clocked at 64 MHz
- Effectively 256 MHz, interleaved 4x
- Output is premodulated to a 64 MHz carrier
Digital CDMA receiver chip
- Data recovery
- PN/Walsh decode
- Chip outputs remain DQPSK modulated, 19b I/Q samples at 1 MHz
- Timing recovery
- Locks on PN-pilot tone correlation peak
- 256 MHz delay locked loop (4 nsec sample-point adjustment)
- Maximum error of 1/8 chip period
- Controllable loop bandwidth/update cycle
- Adjacent cell scan
- 3-tap multipath estimator (for RAKE recovery)
